1. Field of the Invention
The present invention relates to a semiconductor device capable of reducing the device size of a transistor including an offset gate structure, and also relates to a method of manufacturing the semiconductor device.
2. Description of the Related Art
As an example of a conventional method of manufacturing a semiconductor device, the following method of manufacturing an N-channel MOS transistor has been known. Firstly, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. A first silicon oxide film is formed in a portion where a bird's beak with a smooth slope is to be formed in a region of the epitaxial layer where a LOCOS oxide film is to be formed. Then, a second silicon oxide film is formed on the epitaxial layer including the portion of the first silicon oxide film. Thereafter, a silicon nitride film is formed, which includes an opening in a region where the LOCOS oxide film is to be formed. Subsequently, the LOCOS oxide film is formed by means of a LOCOS method. A photoresist is formed on the epitaxial layer as a selection mask, and a P type diffusion layer constituting a drain region is formed by means of an ion implantation technique. At this time, ions of impurity are implanted into a portion below the bird's beak with a smooth slope of the LOCOS oxide film, so that a P type diffusion layer is formed. After that, a back gate region, a source region, a gate oxide film and a gate electrode are formed. As a result, the N-channel MOS transistor is manufactured. This technology is described for instance in Japanese Patent Application Publication No. 2003-309258 (Pages 5 and 6, and FIGS. 5 to 8).
As an example of a conventional semiconductor device, the following LOCOS offset P-channel MOS transistor has been known. In a region where the P-channel MOS transistor is to be formed, an N type well region, which is to be used as a back gate region, is formed in a P type substrate by mean of an ion implantation technique using a resist mask. Then, a P type low-concentration diffusion layer, which is to be used as a drain region, is formed in the N type well region by means of the ion implantation technique using a resist mask. Thereafter, a LOCOS oxide film is formed by means of a LOCOS method in the P type substrate, and then a gate oxide film and a gate electrode are formed on the P type substrate. Subsequently, P type high-concentration diffusion layers, which are to be used as a source region and a drain region, are formed in the P type substrate by means of the ion implantation technique using a resist mask. As a result, the P-channel MOS transistor is manufactured. This technology is described for instance in Japanese Patent Application Publication No. 2003-324159 (pages 26 to 30, and FIGS. 1 to 3).
When a LOCOS offset MOS transistor is manufactured with the conventional method of manufacturing a semiconductor device, the step of forming a diffusion layer as a drain region is performed before the step of forming a gate electrode, as described above. In other words, the diffusion layer as the drain region is formed by means of the ion implantation technique using a photoresist mask in which an opening is selectively formed. Accordingly, in the case of this manufacturing method, it is necessary to take account of mask misalignment in the step of forming the diffusion layer as the drain region. For this reason, it is difficult to reduce a device size.
Moreover, in the conventional method of manufacturing a semiconductor device, the diffusion layer as the drain region is formed by means of the ion implantation technique using the photoresist mask in which the opening is selectively formed. Then, the gate electrode is formed by using the photoresist mask in which the opening is selectively formed. In this manufacturing method, mask misalignment occurs in each step, leading to a reduction in the channel length. For this reason, it is difficult to obtain desired MOS transistor characteristics. Moreover, in order to avoid the reduction in the channel length, a margin needs to be provided for the mask misalignment, in turn making it difficult to reduce the device size of the MOS transistor, as described above.
Furthermore, in the conventional method of manufacturing a semiconductor device, the diffusion layers as the drain region and the source region are formed by means of the ion implantation technique using the photoresist mask in which the opening is selectively formed. When the drain region is formed on each side of the source region, a mask misalignment produces a longer separation distance between the drain and source regions on one side while producing a shorter separation distance between the drain and source regions on the other side. For this reason, even such a reduced separation distance between the drain and source regions needs to have a desired separation distance therebetween. Accordingly, it is necessary to take account of an extra margin for mask misalignment. As a result, there is a problem that it is difficult to reduce the device size of a MOS transistor, and also to reduce the on-resistance of the MOS transistor.